module  led(
    input               clk,
    input               rst_n,
    input               din,
    output   reg [0:0]  led=1'b0
);
    always @(*)begin
        if(din==1'b0)begin
            led<=1'b0;
        end
        else if(din==1'b1)begin
            led<=1'b1;
        end
        else begin
            led<=led;
        end
    end



endmodule